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Antmicro

Antmicro is a software-driven tech company developing open and modern industrial edge and cloud AI systems.

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  1. jetson-orin-baseboard jetson-orin-baseboard Public

    Baseboard targetting the NVIDIA Jetson Orin Nano and Jetson Orin NX

    204 54

  2. renode renode Public

    Forked from renode/renode

    Renode - virtual development tool for multinode embedded networks

    RobotFramework 38 3

  3. tensorflow-arduino-examples tensorflow-arduino-examples Public

    TensorFlow Lite Micro examples built in collaboration between Google and Antmicro, runnable in Google Colab and with Renode CI tests

    Shell 25 4

  4. fastvdma fastvdma Public

    Antmicro's fast, vendor-neutral DMA IP in Chisel

    Scala 129 27

  5. polarfire-som polarfire-som Public

    System on Module based on Microchip PolarFire MPFS250T SoC

    22 11

  6. jetson-agx-thor-baseboard jetson-agx-thor-baseboard Public

    Open hardware baseboard for Nvidia Jetson Thor AGX T5000 System on Module

    19 5

Repositories

Showing 10 of 832 repositories
  • renode-vscode-extension Public
    antmicro/renode-vscode-extension’s past year of commit activity
    TypeScript 8 Apache-2.0 0 0 0 Updated Feb 2, 2026
  • bazel_rules_hdl Public Forked from hdl/bazel_rules_hdl

    Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)

    antmicro/bazel_rules_hdl’s past year of commit activity
    Starlark 0 Apache-2.0 62 0 0 Updated Feb 2, 2026
  • cros-platform-ec-tester Public
    antmicro/cros-platform-ec-tester’s past year of commit activity
    RobotFramework 1 Apache-2.0 2 1 2 Updated Feb 2, 2026
  • verilator Public Forked from verilator/verilator

    Verilator open-source SystemVerilog simulator and lint system

    antmicro/verilator’s past year of commit activity
    SystemVerilog 22 757 0 0 Updated Feb 2, 2026
  • verilator-verification Public

    Test dashboard for verification features in Verilator

    antmicro/verilator-verification’s past year of commit activity
    SystemVerilog 29 Apache-2.0 5 1 0 Updated Feb 2, 2026
  • topwrap Public

    A Python package for generating HDL wrappers and top modules for HDL sources

    antmicro/topwrap’s past year of commit activity
    Python 56 Apache-2.0 7 1 0 Updated Feb 2, 2026
  • f4pga-arch-defs Public Forked from f4pga/f4pga-arch-defs

    FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

    antmicro/f4pga-arch-defs’s past year of commit activity
    Jupyter Notebook 1 ISC 123 0 10 Updated Jan 31, 2026
  • sv-tests Public Forked from chipsalliance/sv-tests

    Test suite designed to check compliance with the SystemVerilog standard.

    antmicro/sv-tests’s past year of commit activity
    SystemVerilog 2 ISC 89 0 22 Updated Jan 30, 2026
  • busperf Public

    Bus performance analysis tool

    antmicro/busperf’s past year of commit activity
    Rust 11 Apache-2.0 0 0 0 Updated Jan 30, 2026
  • trace2power Public
    antmicro/trace2power’s past year of commit activity
    Rust 8 Apache-2.0 1 1 0 Updated Jan 31, 2026
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